Method and apparatus of automatic power management control for serial ATA device directly attached to SAS/SATA host controller

ABSTRACT

The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA device directly attached to a SAS/SATA host controller. In an exemplary aspect of the present invention, it is determined whether a Serial ATA device is directly attached to a SAS/SATA host controller without using a SAS expander. When it is determined that the Serial ATA device is directly attached to the SAS/SATA host controller, an idle or active condition of a Serial ATA interface including the Serial ATA device and the SAS/SATA host controller is automatically detected. When the Serial ATA interface is in an idle condition, idle time of the Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state. When a power down counter value is equal to a second value, a request for a Slumber power state is asserted, and Serial ATA interface is put into a Slumber power state.

CROSS-REFERENCE TO RELATED DOCUMENTS

The present application is a continuation-in-part of U.S. applicationSer. No. 10/606,138, entitled Method And Apparatus Of Automatic PowerManagement Control For Serial ATA Interface, filed Jun. 25, 2003 nowU.S. Pat. No. 7,028,199, which is herein incorporated by reference inits entirety.

The present application herein incorporates U.S. patent application Ser.No. 10/901,519 entitled: “Method and Apparatus of Automatic PowerManagement Control for Serial ATA Interface Utilizing a Combination ofIOP Control and Specialized Hardware Control” filed Jul. 29, 2004,(pending) and U.S. patent application Ser. No. 10/901,520 entitled:“Method and Apparatus of Automatic Power Management Control for NativeCommand Queuing Serial ATA Device” filed Jul. 29, 2004, (pending) bothfiled on the same day as the present patent application, by reference intheir entirety.

FIELD OF THE INVENTION

This invention relates generally to power management control, andparticularly to a method and apparatus of automatic power managementcontrol for a Serial ATA device directly attached to a SAS/SATA hostcontroller.

BACKGROUND OF THE INVENTION

Serial ATA (Advanced Technology Attachment) is an evolutionaryreplacement for the Parallel ATA physical storage interface. Serial ATA(SATA) is a computer bus primarily designed for transfer of data betweena computer processor and hard disk and has at least three advantagesover Parallel ATA, namely speed, cable management, and Serial ATA'sability of being hot swappable.

There are three interface power states supported in Serial ATA:PhyReady, Partial and Slumber. In PhyReady (or power up) state, the PHY(physical) logic and main PLL (phase-locked loop) are both on andactive, and the interface is synchronized and capable of receiving andsending data. Partial and Slumber are two power saving (or power down)modes. In both Partial and Slumber states, the PHY logic is powered, butis in a reduced power state. However, while the exit latency fromPartial state is generally no longer than 10 μs (microseconds), the exitlatency from Slumber state is generally no longer than 10 ms(milliseconds).

When a Serial ATA interface is idle (i.e., when either a Serial ATA hostcontroller or a Serial ATA device is not active) for a period of time,it is desirable to put the interface into a power saving mode. Inaddition to saving power while in a power saving mode, the interfacelifetime may be increased.

With the adoption of the Serial Attached SCSI (SAS) protocol, it ispossible to create a SAS/SATA host controller, to which a SATA device(e.g., a SATA drive or the like) may be either directly attached oraccessed through a SAS Expander via the SCSI Tunneling Protocol (STP).In other words, a SAS/SATA host controller supports both SAS and SATA,and a SATA device may be either directly attached to the SAS/SATAcontroller or may be attached to a SAS expander that is attached to theSAS/SATA controller. In the case where the SATA device is attached viathe expander, the host controller uses the SAS STP protocol to accessthe device. In this case, no SATA power management is allowed per theSAS specification. On the other hand, in the case where the SATA deviceis directly attached to the host controller, SATA power management isallowed.

Thus, it would be desirable to provide a method and apparatus ofautomatic power management control for a Serial ATA device directlyattached to a SAS/SATA host controller.

SUMMARY OF THE INVENTION

In an exemplary aspect of the present invention, it is determinedwhether a Serial ATA device is directly attached to a SAS/SATA hostcontroller without using a SAS expander. When it is determined that theSerial ATA device is directly attached to the SAS/SATA host controller,an idle or active condition of a Serial ATA interface including theSerial ATA device and the SAS/SATA host controller is automaticallydetected. When the Serial ATA interface is in an idle condition, idletime of the Serial ATA interface is measured using a power down counterwhose frequency is determined by a programmable register based on aninput clock. When a power down counter value is equal to a first value,a request for a Partial power state is asserted, and Serial ATAinterface is put into a Partial power state. When a power down countervalue is equal to a second value, a request for a Slumber power state isasserted, and Serial ATA interface is put into a Slumber power state.

The apparatus of the present invention may put the Serial ATA interfaceinto power up and power down states automatically. Because the presentinvention automatically detects the interface idle condition and putsthe interface into a power saving mode when the interface is in idlecondition for a programmable period of time, the present invention maysave power and increase the interface lifetime. Moreover, because thepresent invention controls the power state change of the Serial ATAinterface by hardware, communications with high level layers of theinterface is avoided, which may lead to an efficient power savingmethod.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory onlyand are not restrictive of the invention as claimed. The accompanyingdrawings, which are incorporated in and constitute, a part of thespecification, illustrate an embodiment of the invention and togetherwith the general description, serve to explain the principles of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

The numerous advantages of the present invention may be betterunderstood by those skilled in the art by reference to the accompanyingfigures in which:

FIG. 1 is a flow diagram showing a method of automatic power managementcontrol for a Serial ATA device directly attached to a SAS/SATA hostcontroller in accordance with an exemplary embodiment of the presentinvention;

FIG. 2 is a flow diagram showing a method of automatic power managementcontrol for a Serial ATA device directly attached to a SAS/SATA hostcontroller in accordance with a further exemplary embodiment of thepresent invention;

FIG. 3 is a schematic block diagram illustrating an apparatus ofautomatic power management control for a Serial ATA interface inaccordance with an exemplary embodiment of the present invention,wherein the apparatus includes a serial ATA device, a SAS/SATA hostcontroller, and automatic power management circuitry in accordance withan exemplary embodiment of the present invention; and

FIG. 4 is a schematic block diagram illustrating an exemplary embodimentof the automatic power management circuitry shown in FIG. 3 inaccordance with an exemplary embodiment of the present invention,wherein the Timer Count Reg, the Partial Count Reg, the Slumber CountReg, and the Firmware Control Reg are not shown.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the presently preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings.

Referring first to FIG. 1, a method or process 100 of automatic powermanagement control for a Serial ATA device directly attached to aSAS/SATA host controller in accordance with an exemplary embodiment ofthe present invention is shown. The process 100 starts with a step 102,in which it is determined whether a Serial ATA device is directlyattached (i.e., without using a SAS Expander or the like) to a SAS/SATAhost controller. It is understood that a SAS/SATA host controllersupports both SAS and SATA, and a SATA device may be either directlyattached to the SAS/SATA controller or may be attached to a SAS expanderthat is attached to the SAS/SATA controller. Per the SAS standard, ablock of a PHY logic of the SAS/SATA host controller may determinewhether the SATA device is directly attached to the controller orwhether the device is attached via a SAS Expander. Those of ordinaryskill in the art will understand that other means may be used todetermine whether a Serial ATA device is directly attached to a SAS/SATAhost controller without departing from the scope and the spirit of thepresent invention. When it is determined that the Serial ATA device isdirectly attached to the SAS/SATA host controller, an idle condition ofa Serial ATA interface including the Serial ATA device and the SAS/SATAhost controller is detected 104. Next, idle time of the Serial ATAinterface is measured 106. Then, the Serial ATA interface is placed intoPartial power state when the measured idle time is equal to a firstvalue 108. Next, the Serial ATA interface is placed into Slumber powerstate when the measured idle time is equal to a second value 110. In apreferred embodiment of the present invention, the second value isalways greater than the first value. That way, when both power savingmodes are supported and enabled, the present invention ensures that theSerial ATA interface is first placed into Partial State, followed bySlumber. It is understood that other embodiments may be contemplated bya person of ordinary skill in the art without departing from the scopeand spirit of the present invention. For example, in an alternativeembodiment of the steps 106 and 108, the Serial ATA interface may beplaced into a power saving mode when the measured idle time is equal toa predetermined value, wherein the power saving mode is either a Partialpower state or a Slumber power state.

Referring to FIG. 2, a method or process 200 of automatic powermanagement control for a Serial ATA device directly attached to aSAS/SATA host controller in accordance with a further exemplaryembodiment of the present invention is shown. According to the presentinvention, there may be three programmable registers: Timer Count Reg,Partial Count Reg, and Slumber Count Reg. Timer Count Reg holds aprogrammable value TimerCount, which determines the frequency for apower down counter (pd_ctr). For example, based on the frequency of theinput clock, Timer Count Reg may be programmed accordingly to obtain thetime period such as 1 ms, 2 ms, or the like for the pd_ctr. PartialCount Reg holds a programmable non-zero value PartialCount. When apd_ctr value is equal to PartialCount, a request for Partial state(ReqPartial) is asserted. Slumber Count Reg holds a programmablenon-zero value SlumberCount. When a pd_ctr value is equal toSlumberCount, a request for Slumber state (ReqSlumber) is asserted.

According to process 200, an input clock counter (clk_ctr) counts theclock (step 202) and checks against TimerCount (step 204) to generatethe required frequency to operate the pd_ctr. In step 204, when theclk_ctr value is equal to TimerCount, process 200 proceeds to steps 205and 206 simultaneously. In step 205, the counter clk_ctr is reset, andprocess 200 then returns to step 202.

In step 206, it is determined whether a Serial ATA device is directlyattached (i.e., without using a SAS Expander or the like) to a SAS/SATAhost controller. In step 206, when it is determined that the Serial ATAdevice is directly attached to the SAS/SATA host controller, anidle/active condition of an Serial ATA interface including the SerialATA device and the SAS/SATA host controller is also automaticallydetected. According to one aspect of the present invention, theinterface is active if any of the following conditions is true: (1) BSY,DRQ, or ERR bit of ATA task file register is ON; (2) COMWAKE or COMRESETOOB (out of band) signal is detected; and (3) firmware is forcing theinterface wakeup from a power saving mode by writing a Firmware ForcingWakeUp bit in automatic power management circuitry. If none of theforegoing conditions is true, then the interface is not active (i.e.,idle).

When the interface is detected to be active or the Serial ATA device isnot directly attached, process 200 proceeds to step 208, in which anypower down requests (ReqPartial and/or ReqSlumber) are de-asserted andthe pd_ctr is reset. After step 208, process 200 returns to step 206.

When the interface is detected to be inactive and the Serial ATA deviceis directly attached, process 200 proceeds to step 210, in which thepd_ctr starts to count the interface idle time. Next, in step 212, thepd_ctr value is checked against SlumberCount. If the pd_ctr value isequal to SlumberCount, then in step 214, Slumber Request may bereceived. Next, in step 216, ReqSlumber is ON (asserted), and ReqPartialis OFF (not asserted). Thus, the interface may be placed into Slumberstate.

Following step 212, if the pd_ctr value is not equal to SlumberCount,then in step 218, the pd_ctr value is checked against PartialCount. Ifthe pd_ctr value is not equal to PartialCount, process 200 returns tostep 206. If the pd_ctr value is equal to PartialCount, then in step220, Partial Request may be received. Next, in step 222, ReqPartial isON (asserted), and ReqSlumber is OFF (not asserted). Thus, the interfacemay be placed into Partial state.

In a preferred embodiment of the present invention, SlumberCount isalways greater than PartialCount. Thus, when both power saving modes aresupported and enabled, the present invention ensures that ReqPartial isasserted first, followed by a ReqSlumber. It is understood that otherembodiments may be contemplated by a person of ordinary skill in the artwithout departing from the scope and spirit of the present invention.

FIG. 3 is a schematic block diagram illustrating an apparatus 300 ofautomatic power management control for a Serial ATA interface inaccordance with an exemplary embodiment of the present invention. Themethod 100 shown in FIG. 1 and the method 200 shown in FIG. 2 may beimplemented and executed by the apparatus 300. The apparatus 300includes a SAS/SATA host controller 302, a Serial ATA device 304, andautomatic power management circuitry 306. The SAS/SATA host controller302 supports both SAS and SATA, and a SATA device may be either directlyattached to the SAS/SATA controller 302 or may be attached to a SASexpander that is attached to the SAS/SATA controller 302. In FIG. 3, theSerial ATA device 304 is shown to be directly attached to the SAS/SATAhost controller 302 via Serial ATA cables 308. Those of ordinary skillin the art will understand that the Serial ATA host controller 302 andthe Serial ATA device 304 each have its own physical (PHY), link,transport, and application layers (not shown).

In an exemplary embodiment, the automatic power management circuitry 306may include a Firmware Control Reg 310 and three programmable registers(Timer Count Reg 312, Partial Count Reg 314, Slumber Count Reg 316). Ina preferred embodiment, the Firmware Control Reg 310 is a 32-bitregister, whose Bit0 is a Firmware Forcing Slumber bit, Bit1 is aFirmware Forcing Partial bit, and Bit2 is a Firmware Forcing WakeUp bit.The automatic power management circuitry 306 detects the active/idlecondition of the Serial ATA host controller 302 through BSY, DRQ, andERR Bits and may issue power down requests (ReqPartial and ReqSlumber)to the physical layer of the Serial ATA host controller 302. Theautomatic power management circuitry 306 may also issue ReqPartialand/or ReqSlumber to the physical layer of the Serial ATA hostcontroller 302 when it receives power down requests from the Serial ATAdevice 304.

It is understood that FIG. 3 is intended as an example of apparatus ofautomatic power management control for a Serial ATA interface inaccordance with the present invention and not as an architecturallimitation to the present invention. Those of ordinary skill in the artwill appreciate that various combinations and arrangements may beemployed without departing from the scope and spirit of the presentinvention. For example, the SAS/SATA host controller 302 in FIG. 3 maybe directly connected to more than one Serial ATA device. In oneembodiment, a SAS/SATA host controller may have two ports Port 1 andPort 2, which are connected to Serial ATA devices Device 1 and Device 2,respectively. In this case, according to the present invention, for eachport there may be independent, identical automatic power managementcircuitry. If Port 1 of the host controller and Device 1 are in idlestate, then only Port 1 and Device 1 may be put into a power savingstate, but not Port 2 and Device 2 (assuming Port 2 and Device 2 are inactive state). In addition, the Timer Count Reg 312, the Partial CountReg 314, the Slumber Count Reg 316, and the Firmware Control Reg 310 maybe physically located outside the automatic power management circuitry306.

FIG. 4 is a schematic block diagram illustrating an exemplary embodimentof the automatic power management circuitry 306 shown in FIG. 3 inaccordance with an exemplary embodiment of the present invention,wherein the Timer Count Reg, the Partial Count Reg, the Slumber CountReg, and the Firmware Control Reg are not shown. The method 100 shown inFIG. 1 and the method 200 shown in FIG. 2 may be implemented in theautomatic power management circuitry 306. The circuitry 306 may includea first OR gate 402, a second OR gate 404, a first AND gate 405, aninverter 406, power down counter logic 408 (for counting idle time of aSAS/SATA host controller and comparing a power down counter valueagainst PartialCount/SlumberCount), a second AND gate 409, and powerdown/up circuitry 410 (for issuing a power down or power up request tothe SAS/SATA host controller physical layer).

The OR gate 402 receives BSY Bit, DRQ Bit, and ERR Bit as input andoutputs a value (“1” or “0”, where “1” means a Serial ATA hostcontroller is active, and “0” means a SAS/SATA host controller is notactive) to both the inverter 406 and the OR gate 404 as input. When theOR gate 402 outputs “0”, a SAS/SATA host controller is not active, theinverter 406 outputs “1” which enables the power down counter logic 408.When the power down counter value reaches PartialCount or SlumberCount,and when the Serial ATA device is directly attached, as indicated by theoutput of the AND gate 409, the power down/up circuitry 410 issues apower down request to the Serial ATA Physical Layer. Consequently, apower down state of the SAS/SATA host controller may result.

The OR gate 404 receives as input an output from the OR gate 402, aFirmware Forcing WakeUp Bit, and an COMWAKE or COMREST OOB signal andmay output a WakeUp signal to the power down/up circuitry 410, which inturn issues a power up request to the Serial ATA Physical Layer.Consequently, a power up state of the SAS/SATA host controller mayresult.

In addition, as indicated by the output of the AND gate 405, when theSerial ATA device is directly attached, a Firmware Forcing Partial Bitor a Firmware Forcing Slumber Bit may enable the power down/up circuitry410 to issue a power down request to the Serial ATA Physical Layer,resulting in a power down state of the SAS/SATA host controller.

The present invention may place a Serial ATA interface into power up andpower down states automatically by its own. The apparatus of the presentinvention may automatically detect the interface idle condition and putthe interface into a power saving mode when the interface is in idlecondition for a programmable period of time. Thus, the present inventionmay save power and increase the interface lifetime. Moreover, becausethe present invention controls the power state change of the Serial ATAinterface by hardware, communications with high level layers of theinterface is avoided, which may lead to an efficient power savingmethod.

It is appreciated that the present invention is not limited to a SerialATA interface. The present invention may also apply to a variety ofother interfaces as may be contemplated by a person of ordinary skill inthe art.

It is understood that the specific order or hierarchy of steps in theprocesses disclosed is an example of exemplary approaches. Based upondesign preferences, it is understood that the specific order orhierarchy of steps in the processes may be rearranged while remainingwithin the scope of the present invention. The accompanying methodclaims present elements of the various steps in a sample order, and arenot meant to be limited to the specific order or hierarchy presented.

It is believed that the present invention and many of its attendantadvantages will be understood by the foregoing description. It is alsobelieved that it will be apparent that various changes may be made inthe form, construction and arrangement of the components thereof withoutdeparting from the scope and spirit of the invention or withoutsacrificing all of its material advantages. The form herein beforedescribed being merely an explanatory embodiment thereof, it is theintention of the following claims to encompass and include such changes.

1. An apparatus, comprising: means for determining whether a Serial ATAdevice is directly attached to a SAS/SATA host controller without usinga SAS expander; a counter, communicatively coupled to said means fordetermining, for counting idle time of a Serial ATA interface includingsaid Serial ATA device and said SAS/SATA host controller when saidSerial ATA device is directly attached to said SAS/SATA host controller;a first programmable register holding a first value, said firstprogrammable register communicatively coupled to said counter; a secondprogrammable register holding a second value, said second programmableregister communicatively coupled to said counter; automatic powermanagement circuitry communicatively coupled to said Serial ATAinterface; and a third programmable register programmed based on inputclock to determine frequency of said counter, wherein said automaticpower management circuitry issues a request for Partial power state to aphysical layer of said Serial ATA interface when a value of said counteris equal to said first value, and issues a request for Slumber powerstate to a physical layer of said Serial ATA interface when a value ofsaid counter is equal to said second value.
 2. apparatus of claim 1,wherein said means for determining is a block of a PfIY logic of saidSAS/SATA host controller.
 3. The apparatus of claim 1, wherein saidsecond value is greater than said first value.
 4. The apparatus of claim1, wherein said automatic power management circuitry comprising: a firstOR logic gate receiving BSY Bit, DRQ Bit and ERR Bit as input andoutputting a third value indicating said Serial ATA interface being idleor active; an inverter logic gate receiving said third value as inputand outputting a fourth value to power down counter logic comprisingsaid counter, wherein said Serial ATA interface being idle enables saidpower down counter logic to count down said idle time; and power down/upcircuitry communicatively coupled to said power down counter logic,wherein said power down/up circuitry issues a request for Partial powerstate to said physical layer of said Serial ATA interface when a valueof said counter is equal to said first value and when said Serial ATAdevice is directly attached to said SAS/SATA host controller, and issuesa request for Slumber power state to said physical layer of said SerialATA interface when a value of said counter is equal to said second valueand when said Serial ATA device is directly attached to said SAS/SATAhost controller.
 5. The apparatus of claim 4, wherein when said SerialATA device is directly attached to said SAS/SATA host controller, aFirmware Forcing Partial Bit enables said power down/up circuitry toissue a request for Partial power state to said physical layer of saidSerial ATA interface, and a Firmware Forcing Slumber Bit enables saidpower down/up circuitry to issue a request for Slumber power state tosaid physical layer of said Serial ATA interface.
 6. apparatus of claim5, wherein said Firmware Forcing Partial Bit and said Firmware ForcingSlumber Bit are stored in a fourth register.
 7. The apparatus of claim4, wherein said automatic power management circuitry further comprising:a second OR logic gate receiving said third value, Firmware ForcingWakeUp Bit, and a COMWAKE or COMRESET OOB signal as input, wherein saidsecond OR logic gate outputs a WakeUp signal for disabling a power downrequest to said power down/up circuitry when said third value indicatessaid Serial ATA interface is active, said Firmware Forcing WakeUp Bit iswritten in said automatic power management circuitry, and/or saidCOMWAKE or COMRESET OOB signal is detected; wherein said power down/upcircuitry de-asserts a power down request when said power down/upcircuitry receives said WakeUp signal.